1. Field of the Invention
This invention generally relates to cache memories in computer systems and, more specifically, relates to a method for increasing the address space of memory locations which can be stored in a second level cache.
2. Description of the Related Art
A low cost second level cache subsystem is often included in personal computer systems to improve the effective speed of memory accesses. The memory devices associated with second level caches normally comprise multiple Static Random Access Memories (SRAMs) to hold data, and one or more SRAMs to hold control fields knows as Tag Fields. There is one Tag Field associated with each data entry or line in the cache. Each Tag Field comprises an address field which holds address bits that are used to associate a cache line with a particular main memory location, and a control field with two status bits that indicate whether the associated line holds valid data (Valid bit) and, in a writeback cache, whether that line has been modified in cache, but not in main memory (Dirty bit).
To allow a second level cache to hold data from any addressable memory location, the width of the tag address field must be sufficient to hold the number of address bits corresponding to the number of bits above the address space addressable directly by the cache. For instance, for a typical 128 Kbyte direct map cache used in a system that employs 32 bit addresses, A[0] through A[16] (17 bits) address the 128 Kbyte in the cache, and the tag address field must hold the values of A[17] through A[31] (15 bits). However, in Personal Computer (PC) systems, in order to reduce both cost and pin count, the width of the Tag Field including both address and control bits is often limited to that of a single 8 or 9 bit SRAM. The effect of limiting the number of tag address bits is to reduce the memory address range over which the cache is operative. For instance, if the same 128 Kbyte direct map cache above uses an eight bit SRAM for the Tag Field that holds six tag address bits and the Valid and Dirty status bits, then the tag address field must hold the values of A[17] through to A[22]. For a cache bit to be detected, the cache controller must assume that A[23] to A[31] have some fixed value (normally zero) and the cacheable memory address range is limited to the eight Mbytes represented by the address range from A[0] to A[22].
The system and application software for PCs typically assigns a fixed format for the Tag Field comprising a Valid bit, a Dirty bit, and address bits. This fixed format does not allow the PC to benefit from performance increases that could be achieved if the format of the Tag Field were programmable, increasing the addressable range of the cache in certain circumstances.
Therefore, there existed a need to provide a method of dynamically changing the Tag Field in a second level cache by the system software or by application software to use the status bits as additional address bits to increase the address space accessible to the cache (cacheable address space). This software will have the flexibility of configuring the Tag Field to make tradeoffs concerning cacheable address space, functionality, and performance of the cache.